1. Field of the Invention
The present invention relates to a network path trace apparatus and a network path trace method, and, more particularly, to a network path trace apparatus and a network path trace method which specify the start, middle and end points of a path to be traced to thereby trace the path that extends from the specified start point, through the middle point, to the end point.
2. Description of the Related Art
In designing a digital logic circuit, it is typical practice to extract a signal path connecting two specific points in the circuit and to then make various considerations to the path. For instance, the circuit design requires that a delay of a signal from one point to another point in the circuit be obtained and is verified if it satisfies control conditions of the circuit. The normal operation of the designed logic circuit is thereby ensured. These are very important workings in designing circuits. The verification is executed by extracting a signal path between two points and computing a delay time of a signal along the path.
Large scaling and complication of logic circuits has led to automation of the logic circuit design and has propelled automation of the aforementioned verification. Accordingly, various algorithms are proposed to extract a signal path to be verified from the data of a designed logic circuit (refer, for example, to 15th Design Automation Conference "Design Verification and Performance Analysis"; M, A. Wold; 1978). The extraction of the signal path in these algorithms is achieved by performing a trace process between the specified start and end points based on the mutual coupling relationship of constituent elements of the designed circuit.
Another verification for signal paths may require a middle point of a signal path to be specified in addition to the two (start and end) points required for extracting the path. For instance, in checking whether or not the individual flip-flops in a clock synchronizing type logic circuit satisfy the set up time and hold time conditions, it is necessary to compute the signal propagation delay time of a signal path which extends from a clock signal input terminal of the circuit through one flip-flop A to another flip-flop B. In this case, the start, middle and end points are specified as the clock signal input terminal of the circuit, flip-flop A, and flip-flop B, respectively.
When the start, middle and end points are specified, if the signal path from the start point to the end point is traced in the conventional manner, as shown in FIG. 11, it is not possible to know whether or not the middle point M is passed until the trace starting at start points, reaches the end where the end point E exists. Therefore, trace time would be spent on those many paths among the paths extending from the start point S to the end of the circuit that do not pass the middle point M, thereby deteriorating the tracing efficiency. Particularly with the clock signal input terminal being the start point as per the above example, there are a significant number of coupling destinations, thus the time required for wasteful tracing is increased accordingly. Further, since there are a significant number of combinations in which a flip-flop both serves a the middle point and the end point, the difficulty in tracing the paths for all the combinations and computing the delay time is increased. Furthermore, with the above trace method, the number of branches to be traced increases as the depth of the tracing becomes deeper, as shown in FIG. 11, so that the number of paths to be checked is significantly increased. Therefore, there would be considerable time spent tracing in the case where three points are specified, as per the case where two points are specified.